are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog f.

that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support w.

Table 1-1. S3C8639/C863A Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 (note) P0.4 P0.5 (note) P0.6 (note) P0.7 (note) P1.0 (note) P1.1 (note) P1.2 (note) P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 (note) P2.7 P3.0
  –P3.3 P3.4
  .

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